A Novel IEEE 754 Standard Floating Point Unit Comprising Fused Add-Subtract Unit
In this paper, a high speed and reduced area floating point unit(FPU) is implemented incorporating fused addsubtract unit. The FPU is designed to handle numbers both in single precision and double precision formats. When compared to discrete add-subtract unit, fused add-subtract unit has achieved 33% reduction in area and 52% reduction in delay in case of single precision format. In double precision format compared to discrete add-subtract unit, fused add-subtract unit has achieved a reduction in area and delay by 41% and 40% respectively. The FPU was designed using VHDL language and implemented on a Xilinx Virtex-II FPGA.
Rosemin C.J., Anuja George, Arundev V