Design and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA
An 8-bit Vedic multiplier is improved in terms of transmission delay when compare with the extra predictable multipliers. We have employed 8-bit barrel shifter which craves for only one clock cycle for ‘n’ amount of shifts in our projected design. The arrangement is implemented and checked using FPGA and ISE Simulator. The central part was implemented on Xilinx Spartan-6 family xc6s1x75T-3-fgg676 FPGA. The transmission delay contrast was excerpted from the synthesis report and static timing report too. The structural design might attain propagation delay of 6.781ns by means of barrel shifter in base selection module and multiplier.
B.Madhu Latha, B. Nageswar Rao