DESIGN OF A HIGH FREQUENCY AND LOW POWER SUCCESSIVE APPROXIMATION ADC | Abstract

ISSN ONLINE(2278-8875) PRINT (2320-3765)

Research Article Open Access

DESIGN OF A HIGH FREQUENCY AND LOW POWER SUCCESSIVE APPROXIMATION ADC

Abstract

In this paper, we present the design of a high frequency and low power analog to digital converter (ADC) which operates at 3V power supply using tsmc 0.18micron CMOS technology. The ADC designed is carried out by designing each building block of the circuit separately and then assembling them together to get the required ADC. The CMOS comparator, the digital to analog converter (DAC) and the successive approximation register (SAR) are the key elements in the design of the ADC. The CMOS operational amplifier was designed with a high unity gain frequency that will direct the ADC to operate at a greater speed. Design has been carried out in Tanner EDA tools. Simulation results are verified using S-edit and W-edit.

Priyanka Kakoty, Karen Das

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