Design of Network on Chip with an Arbiter | Abstract

ISSN ONLINE(2320-9801) PRINT (2320-9798)

Research Article Open Access

Design of Network on Chip with an Arbiter

Abstract

Network on Chip (NoC) is one of the solutions for faster on chip communication, possible through routers. This paper presents an NOC with a router containing loopback module, error journal and an arbiter to reduce data loss and congestion. The presented mechanism can distinguish between permanent and transient faults. It can localize and isolate faulty parts in routers of NOC such as bus, input port and output port. This paper is mainly focused on the router design, routing algorithm, and arbitration algorithm and buffer mechanism.

Gopika Santhosh

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