Designing and Simulating a New Full Adder with Low Power Consumption | Abstract

ISSN ONLINE(2278-8875) PRINT (2320-3765)

Research Article Open Access

Designing and Simulating a New Full Adder with Low Power Consumption

Abstract

A full adder circuit, regarding its ability to operate the Elementary Arithmetic, i.e. addition, subtraction, multiplication, and division, is considered as one the most important and applicable parts of digital processors in designing integrated circuits. Hence, the present paper tries to introduce a new full adder cell by the use of carbon Nano-tube transistors technology for achieving a circuit with optimal performance and low power consumption. The proposed design consists of 12 CNTFET transistors which have been connected through the passing transistor logic. Carbon Nano-tube transistors show remarkable advantage over MOSFET transistors in consumption power and performance speed. The simulation of the proposed design was conducted based on CNTFET model and by using HSPICE software with the applying voltage of 0.65V and in three different values of frequency, temperature, and capacitor load. The results revealed that the proposed design bears some advantages over the same circuits presented in previous literature.

A. AsadiAghbolaghi, M.Dolatshahi, M.Emadi

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