Dual Dynamic Node Flip-Flop Design with an Embedded Logic Design
In this paper, we present another dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) focused around DDFF. The proposed designs dispense with the extensive capacitance display in the precharge node of a several state-of-the-art-designs by split dynamic node structure to independently drive the output pull up and pull down transistors. The aim of the DDFF-ELM is to decrease pipeline overhead. It shows an area, power, and speed effective system to join complex logic functions into the flip-flop. The execution examinations made in a 90 nm technology when contrasted with the Semi dynamic flip-flop, with no degradation in speed execution. The leakage power and process voltage-temperature variations of different designs are contemplated in subtle element and are contrasted with the proposed designs.
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