Implementation of Adiabatic Flip Flop And Sequential Circuits Based on CPAL Circuits | Abstract

ISSN ONLINE(2278-8875) PRINT (2320-3765)

Research Article Open Access

Implementation of Adiabatic Flip Flop And Sequential Circuits Based on CPAL Circuits

Abstract

Power consumption is an increasing concern in VLSI circuits. Sharply increasing need for portable electronic devices has reinforced the need of low power design methodologies in the recent years .Adiabatic logic style is proving to be an attractive solution for low power digital design.. In this logic energy is recycled back instead of being wasted. Adiabatic circuitry uses a special type of power supply instead of constant DC supply as in Conventional CMOS logic. These circuits use power-clock voltage in the form of a ramp or sinusoidal signal. This project mainly deals with the implementation of Adiabatic sequential Circuit with CPAL (Complimentary pass transistor adiabatic logic) family & two phase non overlapping clock generator using 0.35 micron technology and Tanner EDA 13.0 tool. This paper proposes implementation of CPAL two phase T flip-flop

Mrs. M.L.Keote, Mrs.S.S.Katre, Mrs. S.N.Joshi ,Mrs. R.S.Keote

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