Low Power L2 Cache Architecture Using Partial Tag Bloom Filter
In this paper, a new cache architecture referred to as Way-Tagged Cache is discussed to improve the energy efficiency of write-through caches. By maintaining the way tags of L2 cache in the L1 cache during read operations, it enables L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. To reduce the energy consumed in tag comparison within highly associative L2 caches a Multistep Tag Comparison method is proposed along with the Partial Tag-Enhanced Bloom Filter to improve the accuracy of cache miss prediction. Similar results are also obtained under different L1 and L2 cache configurations. Simulation results on Altera demonstrate that the proposed technique achieves 50% reduced power consumption along with the reduced area overhead and no performance degradation. Furthermore, the idea of way tagging can be applied to existing low-power cache design techniques to further improve energy efficiency.
C.Gemma Benilda, R.Vijaya Bhasker
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