Performance Evaluation of Digital CMOS Circuits Using Complementary Pass Transistor Network | Abstract

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Performance Evaluation of Digital CMOS Circuits Using Complementary Pass Transistor Network

Abstract

An important issue in the design of VLSI Circuits is the choice of the basic circuit approach and topology for implementing various logic and arithmetic functions such as adders and multipliers. Complementary Pass-transistor Logic (CPL) is the approach to reduce the physical capacitances in a digital circuit and in this way lower the power consumption. Charge-recovery circuitry has the potential to reduce dynamic power consumption in digital systems with significant switching activity. The overall energy-efficiency of charge-recovery circuitry therefore depends on the rate at which transitions occur, yielding an inverse relationship between energy consumption and clock period.This paper mainly focuses on Boost Logic, a charge recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. Complementary Passtransistor Boost Logic(CPBL) is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks PC and ~PC and requires no DC power supply. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, and charge-recovery techniques. In order to achieve low power in adders (Full Adder, Ripple Carry Adder), Multiplexer and Multiplier has been designed using CPBL. The power efficiency obtained using CPBL is 16% lower than CPAL (Complementary Passtransistor Adiabatic Logic). Low power circuits are designed using CPBL is simulated using Tanner EDA 15.1.

C.Kalyana sundaram , A.Palanivel

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