Performance of Flip-Flop Using 22nm CMOS Technology | Abstract

ISSN ONLINE(2320-9801) PRINT (2320-9798)

Research Article Open Access

Performance of Flip-Flop Using 22nm CMOS Technology

Abstract

This paper enumerates low power, high speed design of C2CMOS Flip-Flop. As this flip flop topologies have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flop is analyzed at 22nm technologies. The above designed Flip-Flop is compared in terms of its area, transistor count, power dissipation and propagation delay using DSCH and Microwind tools with C2CMOS Flip-Flop using 90nm. As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance is implemented in layout level which develops the low power consumption chip using recent CMOS micron layout tools

K.Rajasri, A.Bharathi, M.Manikandan

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