DESIGN OF 8-PORT ADAPTIVE NETWORK ON CHIP | Abstract

ISSN ONLINE(2319-8753)PRINT(2347-6710)

Research Article Open Access

DESIGN OF 8-PORT ADAPTIVE NETWORK ON CHIP

Abstract

Networks-on-chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. In this paper, we present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks up-demand.Inaddition, the adaptivity requires a comprehensive, hardly invasive, runtime discernibility infrastructure, i.e., using supervising components, in order to collect data on the system put forward. The area overhead brought in by the adaptive scheme can be traded off against the tractability acquired. furthermore, the area operating cost is also reduced by resource manifolding due to the on-demand buffer assignment at each output port (we achieved on an average 42% buffer saving in our experiments).The proposed network-On-Chip can be modelled using Verilog HDL and simulated using Modelsim software.

A.Prasannah Rajasingh, S.Rajkumar

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