Test Pattern Generation Using BIST Schemes
A Test Pattern Generator (TPG) is used for generating different test patterns in Built-In Self-Test (BIST) schemes. This work generates Multiple Single Input Change (MSIC) vectors in a pattern, applies each vector to a scan chain is an SIC vector. A MSIC-TPG and Accumulator based TPG are designed and developed a reconfigurable Johnson counter and a scalable SIC counter to generate a class of minimum transition sequences. The Test Pattern Generator is flexible to both the test-per-clock and the testper- scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced Multiple Single Input Change sequences have the favorable features of uniform distribution and low input transition density. It also achieves the target fault coverage without increasing the test length. The architecture modifies scan-path structures, and let the Circuit Under Test (CUT) inputs remain unchanged during a shift operation. Compared with the MSIC-TPG, the proposed Accumulator based TPG achieves reduced area and average power consumption during scanbased tests and the peak power in the CUT. By writing VHDL coding, the test patterns are simulated using MODELSIM and the results are validated.
M. Guru Ramalingam, Dr.P.Veena, Dr.R.Jeyabharath
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