Research Article Open Access

A fast – Locking Pulsewidth Controlled Clock Generator for High Speed SOC Applications

Abstract

A fast-locking pulsewidth-controlled clock generator (PWCCG) based on delay locked loop is proposed in this paper. The coarse and fine delay lines and a time-to-digital detector permits the pulsewidth-controlled clock generator (PWCCG) to operate over a wide frequency range. A new dutycycle setting circuit is also presented in this paper that decides the preferred output duty cycle. Result of the proposed circuit achieves suitable for an input operating frequency range at 2 MHz, and an input duty cycle ranging from 30% to 70%, andproduce a programmable output duty cycle ranging from 30% to 66%.

N.Lavanya, S.Sindhu Meenakshi

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