Review Article Open Access

A Review on Low Power Compressors for High Speed Arithmetic Circuits

Abstract

A Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latency and power consumption. In conventional methods, 10T XNOR structure is used for Full adder design. In proposed method, 3T XNOR gate cell is used for Full adder design. Using this 3T XNOR technology, a 4:2 compressor has been designed and the design of a 5:2 compressor is proposed sing 3T XNOR technology which results in 8T Full adder design which reduces the transistor count when compared to conventional full adders. Hence the proposed compressors can remarkably reduces power consumption. In this review article, various architectures and designs of arithmetic circuits are discussed.

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