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Deep Submicron 50nm CMOS Logic Design With FINFET

Abstract

As the deep submicron technology is introduced, it fulfills the need of increase in speed and efficiency by using transistors of smaller size with faster switching rates. The shrink in the size of MOSFETs substantially increases the channel leakage also increasing the power dissipation. The thin body MOSFET is the backbone of FinFET. MOSFET faces problems like short channel effect, power dissipation and current leakage. FinFET is a double gate MOSFET that has two gates to control the channel and offers distinct advantages for scaling to very short gate lengths. The two gates together strongly influence the channel potential, combating the drain impact, and leading to the better ability to shut off the channel current reducing Drain Induced Barrier Lowering (DIBL). The short channel effect (SCE) can be suppressed and the power dissipation can be reduced by decreasing the fin width (Tfin). This paper deals with the comparison of FinFETs (NAND) in 70nm and 50nm technology in different logic styles IG (Independent gate), SG (Short gate) & IG/LP (Hybrid) modes, also it‟s been compared in terms of parameters like power dissipation (μW) and delay (ps). It is observed that the power dissipation (μW) in 50nm technology for SG mode, NAND gate is reduced by 49.15%, when compared to 70nm technology. When compared to 70nm NAND, the 50nm NAND, SG mode dissipates 34.04%, IG mode dissipates 29.55% and IG/LP mode dissipates 18.33% of power. It is also observed that SG mode has least delay because both gates are tied together to have high current drive. When compared to an 70nm NAND, the 50nm NAND, SG mode has 35.18%, IG mode has 61.76% and IG/LP mode has 55.52% of delay.

P.C.Rajashree, Ancy Thomas, Rose Jaria, Jane Precilla, Alfred Kirubaraj

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