ISSN ONLINE(23209801) PRINT (23209798)
M Premkumar^{1}, P Madhukumar^{2}

Related article at Pubmed, Scholar Google 
Visit for more related articles at International Journal of Innovative Research in Computer and Communication Engineering
In this paper a new comparator design is proposed by using parallel prefix tree with Zero Detector as decision module. This comparator reduces the power and area requirements. When compared to normal parallel prefix tree based comparator the power is reduced by 225mw because of usage of zero detectors as the decision module. This area and power efficient structure can be used in modern CPU ALUs for improved performance. The simulation results for both parallel prefix tree alone and parallel prefix tree along with Zero detector were compared. ModelsimAltera 10.1D has been used for simulation of comparators and their power and area analysis was derived by using Xilinx ISE 10.1.
I. INTRODUCTION 
Comparators form key elements in designing a wide range of applications to support scientific computations, signature analysis and test circuits etc. The basic comparator using parallel prefix tree design is shown in figure1. This structure consists of two basic modules: Comparison resolution module and decision module. 
The comparison resolution module divides two input N bit arrays to be compared into two busses namely left bus and right bus each of N bits wide respectively. The decision module in turn decides whether equal, less than or greater than relationship exists between applied inputs for comparison. 
II. OPERATION 
The comparison proceeds from MSB to LSB by comparing A and B, if they are equal 0 is copied on to left and right buses irrespective of bits compared. The process continues till comparison resolution module finds the first unequality. In case of first unequality the current bit compared from A is placed on to the left bus and bit from B is placed in the right bus. The rest of the comparisons were omitted and o s’ were appended for both left and right bus contents. The comparison resolution module therefore structures the left and right buses. In decision module the contents of left bus and right bus are logically ored individually to choose whether A>B, A<B or A=B. If both the left bus and right bus contents after performing logic or operation are equal the decision is A=B else the bus on which logical or yields a 1 is considered as the largest value i.e. if logical or results 1 on left bus the decision is A>B otherwise A<B. 
III. COMPARATOR ARCHITECTURE 
A 32bitcomparator using zero detector as decision module was considered. Figure3 shows the comparators architectural overview. In this case A and B are 32bit inputs 31 down to 0 [N1 down to 0]. For comparison resolution module A and B are the inputs which are compared from MSB to LSB. Here A31 = 0 and B31=0 i.e., A and B are equal, therefore left bus = right bus=0. Proceeding towards LSB i.e. comparing (MSB1) bits A30=1 and B30 =1 since A and B are equal left bus =right bus=0. Coming further towards right i.e. comparing (MSB2) bits A29=0 and B29=1 since A and B are unequal for the first time then left bus=0 and right bus=1. Further comparisons were omitted because A and B are unequal. The rest of the bits in left and right buses were filled with zeros. And further to perform the OR operation for indusial buses and finds comparator result. 
We partition the structure into five hierarchical prefixing sets as depicted with the associated symbols specific function Whose output serves as input to the next set, until the fifth set produces the output on the left bus and the right bus representation in given below the tables. And Logic gate representations for symbols used comparison module implementation. 
The above symbols are usually used in implementation. Each symbol is represented by the corresponding logic gates. The symbol will perform the operation represented by the logic gate and maximum fan in and fan outs are indicated as 2/4 I.e., the maximum number of inputs are 2 and the maximum number of outputs are 4. These symbols are used to implement the several sets of operations. 
In comparison resolution module four sets are used and each set performs different gate operations. In set1 the XOR operation is performed with A and B inputs and the output of the gates is D which is 32 down to 0. Set2 perform the NOR operation. The set1 output is given as input for set2 and each gate has 4 inputs with one output. Set3 is similar to set2 (XOR operation). The inverted inputs are applied to NAND gate and its output is also inverted. In decision module set5 performs the multiplexer operation. 
A new comparator design is proposed by using parallel prefix tree with Zero detector as decision module. Zero detector having less number of gates are used compare to decision module. The zero detector is used to check the left bus and right bus. If all bits are zero or not will be check based on the left bus and right bus results we can find the comparator results. 
Given below figure4 shows the designed 32Bit Scalable Digital CMOS Comparator Using Parallel Prefix Tree. In this section, we detail our comparator’s design which is based on using a novel Parallel Prefix Tree. 
The designed 32Bit Scalable Digital CMOS Comparator Using Parallel Prefix Tree with Zero Detector as Decision Module is shown in. 
IV. AREA AND POWER EVALUATIONS 
The 32bit parallel prefix structure is implemented by using the Xilinx ISE 10.1 and ModelsimAltera 10.1D. In Xilinx software, we can show design summary 
i.e., how many LUTs, Flip Flops, slices and gate clocks are used. The figure above shows the device utilization summary. 
The given below the figure is evaluated power for given clock frequency (50 MHz) for the normal prefix tree structure: 
V. CONCLUSION AND FUTURE WORK 
In this paper we present a 32Bit Parallel Prefix Tree Using Zero Detector As Decision Module. This comparator reduces the area and power requirements. ModelsimAltera 10.1D has been used for simulation of comparators and their power and area analysis was derived by using Xilinx ISE 10.1. In feature work we can include the 64bit comparator to reduce the power consumption and area using Parallel Prefix Tree with Zero Detector. 
REFERENCES 
1. Muppala Premkumar, P.Madhu Kumar,, “Scalable Digital CMOS Comparator Using a Parallel Prefix Tree with zero detector”,
International Journal of Engineering Research & Technology (IJERT), ISSN: 22780181,, June 2014, Volume. 3 , Issue. 06, pp.1353
1357 2. H. J. R. Liu and H. Yao, HighPerformance VLSI Signal Processing Innovative Architectures and Algorithms, vol. 2. Piscataway, NJ: IEEE Press, 1998. 3. Y. Sheng and W. Wang, “Design and implementation of compression algorithm comparator for digital image processing on component,” in Proc. 9th Int. Conf. Young Comput. Sci., Nov. 2008, pp. 1337–1341. B. Parhami, “Efficient hamming weight comparators for binary vectors based on accumulative and up/down parallel counters,” IEEE Trans.Circuits Syst., vol. 56, no. 2, pp. 167–171, Feb. 2009. 4. A. H. Chan and G. W. Roberts, “A jitter characterization system using a componentinvariant Vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004. H. Suzuki, C. H. Kim, and K. Roy, “Fast tag comparator using diode partitioned domino for 64bit microprocessor,” IEEE Trans. Circuits Syst. I, vol. 54, no. 2, pp. 322–328, Feb. 2007. 5. D. V. Ponomarev, G. Kucuk, O. Ergin, and K. Ghose, “Energy efficient comparators for superscalar datapaths,” IEEE Trans. Comput., vol. 53, no. 7, pp. 892–904, Jul. 2004. 6. V. G. Oklobdzija, “An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 1, pp. 124–128, Mar. 1994. 7. H. L. Helms, High Speed (HC/HCT) CMOS Guide. Englewood Cliffs, NJ: PrenticeHall, 1989. 8. SN7485 4bit Magnitude Comparators, Texas Instruments, Dallas, TX, 1999. 9. K. W. Glass, “Digital comparator circuit,” U.S. Patent 5 260 680, Feb.13, 1992. 10. D. norris, “Comparator circuit,” U.S. Patent 5 534 844, Apr. 3, 1995. 11. W. Guangjie, S. Shimin, and J. Lijiu, “New efficient design of digital comparator,” in Proc. 2nd Int. Conf. Appl. Specific Integr. Circuits, 1996, pp. 263–266. 12. S. AbdelHafeez, “Single rail domino logic for fourphase clocking scheme,” U.S. Patent 6 265 899, Oct. 20, 2001. 13. M. D. Ercegovac and T. Lang, Digital Arithmetic, San Mateo, CA: Morgan Kaufmann, 2004. 14. J. P. Uyemura, CMOS Logic Circuit Design, Norwood, MA: Kluwer,1999. 