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CMOS Design, Simulation and Physical Design of a Two Channel Demodulator

Elumalai R1, K.M.Vanitha2, ElavaarKazhaliv3
  1. Professor, Dept. of IT, MSRIT, Bangalore, India 1
  2. Assistant Professor, Dept. of IT, MSRIT, Bangalore, India2, 3
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International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

Abstract

In this paper, we present a two channel direct demodulator design for differential signals. The twochannel demodulator accepts two independent input signals in a differential mode and demodulates to provide a filtered DC output. Based on analog multiplexer (AM) select pin, one channel is selected out of 2 channels for the differential signal (v1,v2) processing. Demodulator section consists of precision full wave rectifier (PR), 2ndorder Butterworth low pass filter (AF), and summing & difference amplifiers (SA & DA).The Filtered outputs are added, subtracted & amplified to get -(v1+v2) & (v2-v1) outputs respectively which are of bipolarities. This finds applications in processing signals from differential transformers. The mentioned method of demodulation is much superior to that of synchronous demodulation on parameters of noise performance, phase error, additional clock, components count and accuracy.

Keywords
CMOS amplifiers, Rectifiers, Filters, AnalogLayout

INTRODUCTION
The block diagram of the proposed 2-channel demodulator is as shown in Figure-1. It basically consists of analog multiplexer, operational amplifier, precision rectifiers, active filters,summing and difference amplifiers.Circuit design& simulation of modules were carried and characterized with Cadence Tool. All the modules were integrated and full functionality were verified with the specification as given in Table 1. Layouts of the design completed and verified with Calibre tool.

LITERATURE SURVEY
Mike Donnelly [1] presents a systematic process for developing and examining of Simulink models for Inductive Displacement Transducer (IDT) and signal conditioning circuit. This paper presents a Simulink model based on dual half-wave rectifiers was developed to simulate the behaviour of the signal conditioning circuit. The results of simulation clearly demonstrate the sensitivity and performance at frequency around 4.8KHz.This technique was used in designing an ASIC based demodulator. R.A. Williams [2] and Z.Z. Yu [3][7][8][9] clearly discuss the inductive based imaging and tomographic process for industry which employed the inductive sensing and signal conditioning. Richard Poley [6] in Texas application notes writes about the practical signal conditioning techniques and characteristics of every component in LVDT measurement. This paper also suggest the various means of error correction techniques both hardware and software to improve the sensitivity of the system.

CIRCUIT IMPLEMENTATION
Op-Amp:Due to high gain and high output swing requirement, a 2-stage op-amp had been chosen. The Op-amp has PMOS input differential pair as the 1st gain stage& common source amplifier as 2ndgain stagewith frequency compensation. Cascoded current mirror biasing circuit is used to bias multiple circuits of a 2-stage op-amp. The design specification of the 2-stage op-amp specification is given in Table -2. A schematic diagram is presented in Figure-2 which shows the final design. This circuit is designed especially for low output impedance(~200Ω).The op-amp characteristics such as gain & phase ,slew rate , CMRR ,PSRR ,output swing, output impedance,quiescent current were measured & observed to be as shown in the Table-2. Same op-amp is used for few more blocks in this project.
AnalogMultiplexer: Analog Multiplexer consists of two 2:1 multiplexers with selection logic. Multiplexersare implemented by designing Analog CMOS switches in Transmission Gates (TG) principle. TG provides low ON resistance, less distortion & loss. Op-amp buffer is used at the output of AM to avoid loading effect. Buffers are used for level shifting supply voltage levels from 0&5v to ±5v.Decoderconsists of minimal number of gates& decides which channel to be selected depending on the channel select pin. The characteristics such as rise time,fall time & propagation delay were measured.
Precision Rectifiers:Full Wave precision rectifieris implemented using op-amps whichcancel the forward voltage drop of the diode. So very low level signals (well below the diodes forward voltage) can still be rectified with minimal error. Full Wave precision rectifierprovides a better efficiency (81%).Characteristics of a full wave precision rectifiersuch as ripple factor, form factor were measured.
Active Filters: 2ndorder low pass butter worth filter provides maximally flat pass band response & less ripple (~38mv). 2nd order low pass butter worth filter characteristics such as gain, roll off, cutoff frequency, quality factor etc were designed for the specified input signals.
Summing amplifier & Difference amplifier: The summing amplifiers have been designed with the consideration that the amplifier operates in the linear region even at the maximum output swing. The difference amplifier subtracts the filtered v1 and v2 DC signal. (This difference signal provides magnitude information with polarity). The circuit has been designed with very low input offset to reduce the offset component in the output. The sum & difference outputs fordifferent input voltages were measured & plotted to be as shown in the Table-3.
The graph 1. shows the output of low pass filter after the summer and difference amplifier. It is seen that there is a small difference in theoretical and practical values which is mainly due to the offset voltage of the operational amplifier which in the range of 25nV to 1.7 micro volts in difference amplifier and summer respectively. In spite of this the system delivered output with noise margin less than -33mv.

ANALOG LAYOUT IMPLEMENTATION
Following are the analogue layout techniques that were implemented in this project: Matching Antenna effect, Electro migration, Electrostatic Discharge, Guard Ring, GDSII conversion, Bond Padding, floor plan etc. Design Rule Check(DRC) & layout versus schematic (LVS) are the two verification steps that were carried out using standard EDA tools. The complete layout is as shown below.

CONCLUSION
A 2-channel demodulator for LVDT measurement with low ripple and low offset was design, the design process undertaken was discussed, and the resulting simulation and analysis were presented. It is seen that the resulting ASIC design matched the design specifications.

Tables at a glance
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Table 1 Table 2 Table 3
 

Figures at a glance
Figure 1 Figure 2 Figure 3
Figure 1 Figure 2 Figure 3
 
Graph 1
Graph 1
 

References
  1. Scott Cooper, System Modeling: An Introduction, Mentor Graphics, White paper, Ref. No: MWP2650, www.mentor.com/systemvision, 2006.
  2. Mike Donnelly, LVDT/RVDT Sensor Modeling and Signal Conditioning design, Mentor Graphics, White paper,
  3. www.mentor.com/systemvision, 2006.
  4. R.A. Williams and M.S. Beck (ed.’s), “Process Tomography: Principles, Techniques and Applications” ISBN 0 7506 0744 0, Butterworth Heinemann, 1995.
  5. Z.Z. Yu, A.J. Peyton, W.F. Conway, L.A. Xu and M.S. Beck, “Imaging system based onelectromagnetic tomography (EMT)”, Electronics Letters, 29(7), pp. 625-26, 1993.
  6. S. Al-Zeibak and N.H. Saunders, “A feasibility study of In Vivo electromagnetic imaging”, Phys. Med. Biol., 38, pp. 151-60, 1993.
  7. Richard Poley, Signal Conditioning an LVDT Using a TMS320F2812 DSP, Texas Instruments, Application Report SPRA946, August 2003.
  8. Z.Z. Yu, A.J. Peyton, L.A. Xu and M.S. Beck, “Electromagnetic inductance tomography (EMT): sensor, electronics and image reconstruction for a system with a rotatable parallel excitation field”, IEE Proc. Sci. Meas. Technol., 145(1), pp. 20-25, 1998.
  9. J. Peyton, Z.Z. Yu, G.M. Lyon, S. Al-Zeibak, J. Ferreira, J. Velez, F. Linhares, A.R. Borges,H.L. Xiong, N.H. Saunders and M.S. Beck, "An overview of electromagnetic inductance tomography: description of three different systems", Meas. Sci. Technol., 7, pp. 261-271, 1996.
  10. Z.Z. Yu, P.F. Worthington, S. Stone and A.J. Peyton, “Electromagnetic screening of inductive tomography sensors”, European Concerted Action on Process Tomography conference, Bergen, Norway, ISBN 0 9523165 2 8, pp. 300-10, 1995.