Performance Comparison for Different Configurations of SRAM Cells | Open Access Journals

ISSN ONLINE(2319-8753)PRINT(2347-6710)

Performance Comparison for Different Configurations of SRAM Cells

R. K. Sah1, I. Hussain2, M. kumar3
  1. P.G. Student, Department of ECE, NERIST, Nirjuli, Arunachal Pradesh, India
  2. Assistant Professor, Department of ECE, NERIST, Nirjuli, Arunachal Pradesh, India
Related article at Pubmed, Scholar Google

Visit for more related articles at International Journal of Innovative Research in Science, Engineering and Technology

Abstract

Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other configurations because this structure uses a single bit for both read and write operations. This SRAM cell also provides the least power delay product among different studied SRAM configurations. Performance in terms of power dissipation and power delay product are least for 7T SRAM cell among the other SRAM configurations in 90nm CMOS technology.

Keywords

SRAM, Power, Delay, Power delay product, Write, Read.

INTRODUCTION

The use of SRAM is expected to increase in future for both portable and high performance microprocessor. SRAM
plays a critical role in modern microprocessor system, portable devices like PDA, cellular phones, and portable
multimedia devices [1]. To achieve higher speed microprocessor, SRAM based cache memories are commonly used.
The trend of scaling of device brings several challenges like power dissipation, sub threshold leakage, reverse diode
leakage, and stability [2]. Nowadays research on very low threshold voltage and ultra-thin gate oxide are in progressive
stage, due to reduction in the threshold voltage and the gate oxide thickness. The phenomena like intrinsic parameter
fluctuation, random dopant fluctuation, oxides thickness fluctuation, and line edge roughness further degrade the
stability of SRAM cells [3-5]. Large scale integration and fabrication process has resulted in increased density of
devices by decreasing the device physical dimensions. Performance in terms of low power dissipation and high speed
operation are the major challenges of integrated circuit design in deep submicron and nanoscale technologies.
Designing high performance VLSI chip is becoming necessity for mobile communication and computing devices.
Advances in battery technology have not taken place as fast as advances in the electronic devices and systems. So,
designing electronic systems having high performance in terms of high speed and low power dissipation is a
challenging task.
Low power and high speed circuit design differs from applications to applications. In case of battery operated portable
systems, such as cellular phones and laptops, the overall goal of power minimization using low power circuit design is
to keep the battery lifetime and weight reasonable. For high performance and non battery operated systems, such as
workstations and multimedia digital signal processors, the overall goal of power minimization is to reduce the overall
system cost (cooling, packaging and energy bill) while ensuring long term device reliability. These different
requirements are the driving factors for low power and high speed electronic system design [6-7].
Paper is organized as follows. Different SRAM cell Configurations (6T, 7T, 8T, and 9T) are discussed in section II.
Section III provides performance comparison in terms of power, delay, and power delay product for various types of
SRAM configurations. Finally, conclusion is provided in section IV.

RELATED WORK

Fig.1 shows a 6T SRAM cell [8]. This SRAM cell shows poor stability and has small hold and read static noise
margins. In read operation, the stability decreases because of the voltage division between the access transistor and the
driver transistor. The basic cell of 6T SRAM cell consists of six MOS transistors. This SRAM cell provides less read
noise margin which further degrades due to process variation. To achieve higher read noise margin in 6T SRAM cell,
width of pull down transistors has to be increased which eventually increases the issue of rise in leakage power
dissipation [8]. This SRAM cell consumes more power and shows poor stability for small feature sizes with low
voltage supply. During operation, the stability decreases due to the voltage division between the accesses and driver
transistors.
image
Fig. 1. A 6T SRAM cell
Figure shows a 7T SRAM cell [9]. The 7T SRAM cell has a good read stability and static noise margins. This cell has 7
transistors where only one bit line (BL), one word line (WL) and one read line (RL) is used. For writing into the
memory cell, bit line (BL) and word line (WL) are used by keeping read line (RL) inactive. Similarly, for reading from
memory cell, bit line (BL) and read line (RL) are used and word line is kept inactive [6]. 7T SRAM cell uses only one
bit line, so power required for charging and discharging of one more bit line is reduced.
image
Fig. 2. A 7T SRAM cell
8T SRAM cell gives high noise margin but its write noise margin is very small. Therefore 8T SRAM is more prone to
failure during write operation. Besides this its write time is higher and this cell occupies 30% more space than a
conventional 6T SRAM cell [9]. 9T SRAM cell has high read noise margin, write noise margin and also has small write time. This SRAM cell is more prone to leakage. 8T SRAM and 9T SRAM cells provide higher read noise margin as
compared to 6T SRAM cell. Literature survey reveals that higher performance in terms of power dissipation and power
delay product can be achieved by using 7T SRAM cell.

PERFORMANCE COMPARISON OF DIFFERENT SRAM CELLS

The conventional 6T SRAM and studied 7T SRAM have been compared for the parameters: read delay, write delay,
power dissipation, and power delay product in 90nm CMOS technology at VDD = 1.80V. Table 1 shows the power
dissipation for various operations in 6T and 7T SRAM cells [8]. Similarly, Table 2 shows delay for various operations
in 6T and 7T SRAM cells [8].
Table 1. Power dissipation for various operations in 6T and 7T SRAM cells
image
Table 2. Delay for various operations in 6T and 7T SRAM cells
image
Table 3 shows the power delay product of different SRAM cells at VDD = 1.32V in 90nm CMOS technology [9]. In
battery operated systems, there is a great demand to increase the life time of battery, while in high speed systems, speed
is the major concern. For low power and high speed operations, designers have to concern on both speed and power
dissipation [9]. For such type of system, power delay product is an important parameter. It is observed from Table 3
that 7T SRAM cell gives a lesser power delay product at 1.32V voltage supply in 90nm CMOS technology.
Table 3. Power delay product of different SRAM cells
image

CONCLUSION

Different SRAM configurations: 6T, 7T, 8T, and 9T have been studied for their performance analysis. Literature survey
reveals that 7T SRAM cell has the advantage of higher noise margin and smaller power dissipation in comparison with
other discussed SRAM configurations. The studied results also show that this SRAM cell has the least power delay
product among different SRAM configurations (6T, 7T, 8T, and 9T SRAM configurations) in 90nm CMOS technology.

References

  1. Na, H., and Endoh, T., “A New Compact SRAM Cell by Vertical MOSFET for Low Power and Stable Operation’’, 3rd IEEEInternational Memory Workshop, Monterey, CA, pp. 1-4, 2011.

  2. Jain, S. K., and Agarwal, P., “A Low Leakage and SNM Free SRAM Cell Design in Deep Sub micron CMOS Technology”, 19th InternationalConference on VLSI Design, Hyderabad, India, pp. 495-498, 2006.

  3. Asenov, A., Brown, A. R., Davies, J. H., Kaya, S., and Slavcheva, G. “Simulation of Intrinsic Parameter Fluctuations in Decananometer andNanometer-scale MOSFETs”, IEEE Transactions on Electron Devices, vol. 50, No. 9, pp. 1837-1852, 2003.

  4. T. Mizuno, J. Okamura and A. Toriumi, “Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel DopantNumber in MOSFETs”, IEEE Transactions on Electron Devices, vol. 41, No. 11, pp. 2216-2221, 1994.

  5. Sasaki, H., Ono, M., Yoshitomi, T., Ohguro, T., Nakamura, S., Saito, M., and Iwai, H., “1.5 nm Direct-Tunneling Gate Oxide Si MOSFETs”,IEEE Transactions on Electron Devices, vol. 43, No. 8, pp. 1233-1242, 1996.

  6. Kumar, M., Hussain, M. A., and Paul, S. K., “Performance of a Two Input Nand Gate Using Subthreshold Leakage Control Techniques”,Journal of Electron Devices, Vol. 14, pp. 1161-1169, 2012.

  7. Kumar, M., Hussain, M. A., and Singh, L. K., “Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its PerformanceComparison”, Communications in Computer and Information Science, Springer Berlin Heidelberg, Vol. 142, pp. 458-463, 2011.

  8. Madiwalar, B., and Kariyappa, B. S., “Singe Bit Line 7T SRAM Cell for Low Power And High SNM”, IEEE International Multi-Conferenceon Automation, Computing, Communication, Control and Compressed Sensing, Kottayam ,pp 223-228, 2013.

  9. Singh, S., Arora, N., and Singh, B. P., “Simulation and Analysis of SRAM Cell Structures at 90nm Technology”, International Journal ofModern Engineering Research, Vol.1, No.2, pp. 327-331, 2011.