A Review of System-On-Chip Bus Protocols | Abstract

ISSN ONLINE(2278-8875) PRINT (2320-3765)

Research Article Open Access

A Review of System-On-Chip Bus Protocols

Abstract

This paper gives a brief description of various on-chip bus protocols such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance bus (AHB) and Advanced Extensible Interface (AXI), Wishbone Bus, Open Core Protocol (OCP) and CoreConnect Bus. It gives a brief introduction of high performance system-on-chip bus protocol termed as the master-slave bus (MSBUS). By taking into consideration the inevitable trade-off among area, throughput and energy efficiency, the control bus is developed as low-cost and lowpower bus whereas the data bus is created as a high-throughput full-duplex bus. This on-chip bus protocol is differentiated from other on-chip bus protocols with feature of efficient block data transfer. This MSBUS is an effective bus protocol in many applications such as image processing, computer vision, and wireless communication where it requires less hardware resources and achieves higher performance, especially in block transfer mode. The comparison is made between different protocols with respect to various parameters.

Rohita P. Patil, Pratima V. Sangamkar

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