AUTOMATIC TEST PATTERN GENERATION WITH POWER AWARE EFFORTS AND ITS VALIDATION OF A GIVEN DESIGN (ASIC) USED IN NETWORK APPLICATION
Project paper discussing Design For Testability flow of a given ASIC design. As the technology trends to continuously shrink from small scale integration (SSI) to very large scale integration (VLSI), design for testability is also included more seriously into the ASIC flow. This paper describes what, why and how Design-For-Testability done. Scan insertion is performed on RTL to convert design into scan design. Automatic Test Pattern Generation is done for scan inserted design considering test power and its reduction. And at last pattern validation is performed before it is passed to ATE to detect real defects in the design.