Dynamic Router Design For Reliable Communication In Noc
Technological evolution enables the integration of billions of transistors on a chip. As VLSI technology scales, and processing power continues to improve, inter-processor communication becomes a performance bottleneck. On-chip networks have been widely proposed as the interconnect fabric for high performance SoCs. Recently, NoC architectures are emerging as the candidate for highly scalable, reliable, and modular on-chip communication infrastructure platform. New network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on store and forward technique, loop back mechanism. In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanism are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. To provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.
Mr. G.Kumaran, Ms. S.Gokila, M.E.
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