IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT RADIX-2 FFT USING VHDL
The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It has various numbers of applications in the field of signal processing. The FFT can be designed by radix-2 butterfly algorithm which requires needless computations and data storage. It consumes more power. Using IEEE-754 single precision and double precision floating-point format the Fast Fourier Transform (FFT) for real numbers can be computed which is implemented in hardware FPGA. This paper describes two new architectures for floating-point addition, subtraction and product which are repeatedly used in radix-2 butterfly algorithm. This new architecture reduces computation complexity, data storage, area, and power consumption. The algorithms are simulated using VHDL language.