Implementation on STM-16 Frame Termination VLSI with High-Speed and Low-Power GDI Techniques. | Abstract

ISSN ONLINE(2278-8875) PRINT (2320-3765)

Research Article Open Access

Implementation on STM-16 Frame Termination VLSI with High-Speed and Low-Power GDI Techniques.

Abstract

Many of the current wireline networks are digitalized, In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and appliance data are transferred with a synchronous transfer module (STM). In this system to put together the advanced STM-16 using the CMOS technology in the technique. The STMs are constructed hierarchically with a nested structure. When commerce with the data for high-speed digital services, a nested level of four is required for each STM; that is, the lowest level of container, virtual container, administrative unit (AU), AU group, and STM. The VLSI has two kinds of I/O ports; one serial port operating at 2.5 Gb/s/pin and sixteen 8-b parallel ports operating at 19.5 Mb/s/pin. The high-speed port is connected to the set of connections side, while the lowspeed ports are connected to the fatal sides including tool switches.Using CMOS technique with STM-16 frame termination VLSI, the power utilization during the sampled by is 34 mW, and that for 2.5Gb/s operation is 1.2w at 25 °C.the proposed Gate Diffusion Technique(GDI) allows reducing power consumption, delay and area of digital circuits, while maintaining low difficulty of logic design.A multiplicity of logic gates have been implemented in 0.35 μm technology to compare the GDI technique with CMOS and PTL. A prototype test chip of STM-16 has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI.

G.Gowri Lakshmi, V.Abila, K.Birndhadevi.