Low-Power Design for Embedded Processors
One of the primary objectives in any system advancement would be power savings by incorporating innovative processes; In the case of embedded systems, the application’s program memory consumes an enormous amount of power that could be obviated by a method which would put a dampener on the data bus transition related to the Instruction fetch cycle. In a nutshell, the paper offers an instruction remap-buffer which would critically minimize the power and energy spent on program fetch. The target would be a DSP core on which the new method would be applied and observed for enhancement of instruction fetch energy using standard DSP benchmarks.
D.Haripriya , Dr.C.Govindaraju, Dr.M.Sumathi
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