Minimization of Area & Power Communication Path for On-Chip Networks
Networks-on-Chip (NoC) have been widely proposed as the future communication paradigm for use in the next generation System-on-Chip (SoC). Conventional analytic models for the performance analysis of Network-on-Chip often possess a surplus amount of area and power constraints, where the number and position of processor elements or faulty blocks vary during run time. Indeed, we propose an efficient router which reduces the number of slices and eliminates the use of arbiter which in turn reduces the area. A detailed comparative analysis with the existing method is performed in terms of reliability and power consumption. It is captured in the Verilog Hardware Description Language and is implemented using the FPGA Spartan3 Xc3S400. Moreover, experimental results have confirmed that the proposed system is the most efficient one regarding with its performance.
Mr.M.Arun, Mr.J.Navarajan, Mr.D.Arul Kumar, Ms.R M Premiha