Power Optimization Using Dual Dynamic Node Pulsed Hybrid Flip-Flop Based on Footed Logic | Abstract

ISSN ONLINE(2320-9801) PRINT (2320-9798)

Research Article Open Access

Power Optimization Using Dual Dynamic Node Pulsed Hybrid Flip-Flop Based on Footed Logic

Abstract

Designing a new dual dynamic node hybrid flip-flop (DDFF) and low power 4/5 Counter was based on DDFF using FOOTED logic. The proposed designs eliminate the large capacitance present in the precharge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The DDFF offers a power reduction of up to 62% and 48% compared to the conventional flipflops like Power PC 603 flip-flop and semi dynamic flip-flop. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flipflop. The performance comparisons made in a 90 nm UMC process show a power reduction of 48% compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and delay variations of various designs are compared with the proposed designs. The Footed logic is used to reduce power in the circuits. An efficient power reduction was obtained using footed logic and a single design was used for both counter which is called low power 4/5 counter.

Indumathi.M, A.Jeena Thankachan

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