A High Performance Decimal Matrix Code
Architecture for Improved Reliable Memory

M. Satya sri; K.Jyothi

A High Performance Decimal Matrix Code Architecture for Improved Reliable Memory

M. Satya sri¹ and K.Jyothi²

PG Student [VLSI&ES], Dept. of ECE, GIET, Rajahmundry, India
Assistant professor, Dept. of ECE, GIET, Rajahmundry, India

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Abstract

Protection codes are necessary to shield memory cells, to maintain good quality level of reliability. But, we don’t find any optimized error detection and correction methods. Therefore, in this paper, we present a high performance Decimal Matrix Code to assure the reliability of memory. This protection code utilizes decimal procedure to detect errors, so that more errors were detected and corrected up to 32. Transient multiple cell upsets (MCUs) are major problems in the reliability of memories exposed to radiation environment. To prevent cell upsets from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but they would require higher delay so an efficient ERT (encoder-reuse technique) is proposed to reduce the area overhead of extra circuits, it utilize DMC encoder itself to be part of the decoder.

Keywords

Error correction codes (ECCs), multiple cells upsets (MCUs), memory.

INTRODUCTION

The general idea for achieving error detection and correction is to add some redundant bits (i.e., some extra data) to a message, which receiver can use to check consistency of the delivered message, and to pick up data determined to be corrupt. Error-detection and correction scheme can be either systematic or non-systematic: In a systematic scheme, the transmitter sends the unique data, and attaches a fixed number of redundant bits, based on particular logic. If only the error detection is required, a receiver can check the same logic to the received data bits and compare its output with the receive check bits; if the values do not match, an error has occurred at some point throughout the transmission. Different types of codes used for Error detection and correction. In a system to uses a non-systematic code, the message is transformed into an encoded message that has at least as many bits as that message. Error detection and correction used to reduce the soft errors. Several techniques are used present to gate upsets in memories. For example, the Bose– Chaudhuri–Hocquenghem codes [8], Reed–Solomon codes [9], punctured difference set (PDS) codes [10], and matrix codes has been used to contact with MCUs in memories. Which requires more area, power, and delay overheads since the encoding and decoding circuits are more complex in these complicated codes.

Reed-Muller code [14] is another protection code that is able to detect and correct additional error than a Hamming code. The main drawback of this protection code is its more area and power requirements. Hamming Codes are more used to correct Single Error Upsets (SEU’s) in memory due to their ability to correct single errors through reduced area and performance overhead [13]. Though brilliant for correction of single errors in a data, they cannot correct double bit errors. One more class of SEC-DED codes proposed to detect any number of errors disturbing a single byte. These codes are additional suitable than the conventional SEC-DED codes for protecting the byte-organized memories [15][16]. Though they operate through lesser overhead and are good for multiple error detection, they cannot correct more errors. There are additional codes such as the single-byte-error-correcting, double-byte-error-detecting (SBCDBD) codes that can correct multiple errors as discussed in [10].

The Single-error-correcting, Double-error-detecting and Double-adjacent-error-correcting (SEC-DED-DAEC) code provides a low cost ECC methodology to correct adjacent errors as proposed in [12]. The only drawback through this code is the possibility of miss-correction for a small subset of many errors. AS CMOS technology scales down to nanoscale and memories are combined through an increasing number of electronic systems, the soft error rate in memory cells is increase, especially when memories operate in space environments due to ionizing effects of atmosphere.

Interleaving technique has been used to restrain MCUs. However, interleaving technique may not be practically used in content-addressable memory (CAM), because of the tight coupling of hardware structures from both cells and comparison circuit structures.

Built-in current sensors (BICS) are proposed to assist with single-error correction and double-error detection codes to provide protection against cell upsets, which can only correct two errors in a word. More recently, in 2-D matrix codes (MCs) are proposed to efficiently correct MCUs per word with a low delay and in this word is divided into rows and columns. The bits per row are protected by Hamming code, while parity is added in each column. For the MC Implemented on Hamming, when two errors were detected by Hamming, the vertical syndrome bits were activated so that these two errors can be corrected. As a result, MC is capable of correcting only two errors. In decimal algorithm with Hamming code has been conceived to be applied at software level. It works to detect and correct soft errors by addition of integer values. The results obtained have shown that this approach have a lower delay overhead over other codes.

The contribution of this paper is a novel decimal matrix code (DMC) based on divide-symbol is implemented to provide enhanced memory reliability. The implemented DMC utilized decimal algorithm (decimal integer addition and decimal integer subtraction) to identify errors. By using decimal algorithm is that the error detection capability was maximized so that the reliability of memory was enhanced. Besides, the encoder-reuse technique (ERT) was implemented to minimize the area overhead of extra circuits (encoder and decoder) without disturbing the whole encoding and decoding processes, because ERT use DMC encoder itself to be part of the decoder.

HIGH PERFORMANCE IMPLEMENTATION OF DECIMAL MATRIX CODE

In this section, DMC is used to assure reliability in the presence of MCUs through reduced performance overheads, and a 64-bit word is encoded and decoded as an example based on the proposed techniques.

A. Schematic of Fault-Tolerant Memory

The schematic of fault-tolerant memory is depicted in Fig1. First, during the encoding (write) process, information bits D are giving to the DMC encoder, and the horizontal redundant bits H and vertical redundant bits V are obtained from the DMC encoder. After this encoding process DMC codeword is stored in the memory. If MCUs happen in the memory, these errors can be corrected in the decoding (read) method. Due to the advantage of decimal algorithm, DMC has high fault-tolerant capability. In the fault-tolerant memory, the Encoder Reuse technique was used to decrease the area overhead of extra circuits and will be introduced in the following sections.

B. DMC Encoder

In this DMC, first, the divide-symbol and place-matrix ideas were performed, i.e., the N-bit word was divided into k symbols of m bits (N = k × m), and these symbols were arranged in a k1 × k2 2-D matrix (k = k1 × k2, here the values of k1 and k2 represents the number of rows and columns in the logical matrix respectively). Second, the horizontal redundant bits H were produced by performing decimal integer addition of selected symbols per row. Here, each symbol is regard as a decimal integer

Third, the vertical redundant bits V were obtained by binary operation among the bits per column. It should be noted that both divide-symbol and arrange-matrix are implemented in logical instead of in physical. Therefore, the DMC does not require changing the physical structure of the memory.

To explain the implemented DMC scheme, we have to consider a 64-bit word as an example, as shown in Fig. 2. The cells from D0 to D63 are information bits. This 64-bit word was divided into sixteen symbols of 4-bit. k1 = 2 and k2 = 4 have to select simultaneously. H0–H39 are horizontal check bits; V0 through V31 are vertical check bits. The maximum correction capability (i.e., the maximum size of MCUs can be corrected) and the number of redundant bits are different when the different values for k and m are select. Therefore, k and m must be carefully adjusted to decrease the correction capability and minimize the number of redundant bits. For example, in this case, when k = 2×2 and m = 8, only 1-bit error can be corrected and the number of redundant bits is 80. When k = 4 × 4 and m = 2, 3-bit errors can be corrected and the number of redundant bits is reduced to 32. However, when k = 2 × 4 and m = 4, the maximum correction capability is up to 5 bits and the number of redundant bits is 72. In this paper, in order to enhance the reliability of memory, the error correction capability is first measured,so k = 2 × 8 and m = 4 are utilized to construct DMC.

The horizontal redundant bits H can be obtained by decimal integer addition as follow:

C. DMC Decoder

The DMC decoder is depicted in Fig 4, which is prepared up of the following sub modules, and each executes a particular task in the decoding process: syndrome calculator, error locator, and error corrector. It can be observed from the fig.4 that the redundant bits must be recomputed from the received information bits D’ and compare to the original set of redundant bits in order to obtain the syndrome bits ΔH and S. Then error locator uses ΔH and S to detect and locate which bits some errors occur in. Finally, in the error corrector, these errors can be corrected by inverting the values of error bits.

In the proposed scheme, the circuit area of DMC is minimized with reusing its encoder. This is calling the ERT. The ERT can decrease the area overhead of DMC without disturbing the entire encoding and decoding processes. From Fig 4, it can be practical that the DMC encoder is also reused for obtaining the syndrome bits in DMC decoder. Therefore, the entire circuit area of DMC can be minimized as a result of using the existent circuits of encoder. Besides, the figure shows the proposed decoder with an allow signal En for deciding whether the encoder needs to be a part of the decoder. In other words, the En signal is used for distinguishing the encoder from the decoder, and it is under manage of the write and read signals in memory. Therefore, in the encoding (write) mode, the DMC encoder is only an encoder to execute the encoding operations. However, in the decoding (read) mode, this encoder is employed for computing the syndrome bits in the decoder. These obviously show how the area overhead of extra circuits can be substantially decreased.

PERFORMANCE ANALYSIS

Performance simulation of DMC is carried out successfully with model Sim Altera 6.5e simulator. Simulation and synthesis has been carried out with XILINX ISE.The frequency is 132.258MHZ, the power supply voltage is 1.1Vand delay of 7.038ns, no.of slice flip-flops are 184, 4 input LUTs 326 and no. of IOBS 194 and no. of GCLKS 1.

CONCLUSION

In this method we have implemented the 64-bit decimal matrix code for detection and correction of errors in memories. To avoid MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Newly, matrix codes (MCs) based on hamming codes have been proposed for memory protection. In this implemented system error detection and correction rate was increased compared to 32-bit decimal matrix code.

Figures at a glance


Figure 1	Figure 2	Figure 3	Figure 4

Figure 5	Figure 6	Figure 7	Figure 8

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E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of scaling on neutron induced soft error in SRAMs from an 250 nm to a 22nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527–1538, Jul. 2010.

C. Argyrides and D. K. Pradhan, “Improved decoding algorithm for high reliable reed muller coding,” in Proc. IEEE Int. Syst. On Chip Conf.,Sep. 2007, pp. 95–98.

A. Sanchez-Macian, P. Reviriego, and J. A. Maestro, “Hamming SEC-DAED and extended hamming SEC-DED-TAED codes through selectiveshortening and bit placement,” IEEE Trans. Device Mater. Rel., to be published.

S. Liu, P. Reviriego, and J. A. Maestro, “Efficient majority logic fault detection with difference-set codes for memory applications,” IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148–156, Jan. 2012.

M. Zhu, L. Y. Xiao, L. L. Song, Y. J. Zhang, and H. W. Luo, “New mix codes for multiple bit upsets mitigation in fault-secure memories,”Microelectron. J., vol. 42, no. 3, pp. 553–561, Mar. 2011.

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S. Baeg, S. Wen, and R. Wong, “Interleaving distance selection with a soft error failure model,” IEEE Trans. Nucl. Sci., vol. 56, no. 4, pp.2111–2118, Aug. 2009.