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DESIGN AND PERFORMANCE ANALYSIS OF CARRY SELECT ADDER

Abstract

Minimizing area and power is the more challenging task in modern VLSI design. Adders are the most widely used components in many circuits, the design of area and power efficient high-speed data path logic systems forms the largest areas of research in VLSI system design. The study presents a new dynamic logic named sp-D3L that overcomes the speed limitations of D3L. Power consumption is significantly reduced by using the sp-D3L logic. CSLA is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is span for reducing the area and power consumption in the CSLA.

Bhuvaneswaran.M, Elamathi.K

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