Research Article Open Access

Design of Error Compensation for High Performance Fixed -Width Multiplier

Abstract

A modern approach to design a new error compensation circuit by using the dual group minor input correction vector to lower input correction vector compensation error. By utilizing the symmetric property of the minor input correction vector, the hardware complexity of the error compensation circuit can be lowered. By constructing the error compensation circuit mainly from the “outer” partial products, the hardware complexity only increases slightly as the multiplier input bits increase. In the proposed 16 X 16 bits fixed-width multiplier (Baugh Wooley), the truncation error can be lowered by 91% as compared with the direct-truncated multiplier and the transistor count can be reduced by 53% as compared with the full-length multiplier. As compared with the state-of-the-art design, the proposed fixedwidth multiplier performs not only with lower compensation error but also with lower hardware complexity and power consumption, especially as multiplier input bits increase. The proposed error compensation circuit is designed in VHDL and implemented in XILINX FPGA

K.Dhanalakshmi, M.Thivya, V.R.Arulmozhi, S.Nagendra Prabhu

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