Research Article Open Access

FPGA Implementation of High Speed Linear Convolution Using Vedic Mathematics

Abstract

Convolution is a mathematical operation, just as multiplication, addition. It takes two signals and produces a third signal. Convolution has many applications in Digital Signal Processing and Image Processing. In linear time invarient systems, convolution is used for describing the relationship between three signals, the input signal, the impulse response, and the output signal. Traditionally graphical method is used for finding convolution, which is slow and very time consuming. Vedic algorithms are used since it reduces time, increases speed and is easy to implement. This paper presents an algorithm for computing 4 bit linear convolution using vedic mathematics. The algorithm urdhva triyagbhyam based on vedic mathematics is used. The algorithm is coded in VHDL and synthesized using Spartan 6 device on Xillinx ISE simulator 14.2.

Magdum Sneha. S, Prof. S.C. Deshmukh

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