Research Article Open Access

High Speed IIR Notch Filter Using Pipelined Technique

Abstract

Filters are being designed using the HDL languages to increase their speed. Increase in the speed of the individual block leads to increase in the speed of complete block. Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of Infinite Impulse Response (IIR) notch filter. The basic 2nd ordered notch filter structure is implementable in Xilinx Virtex-5 FPGA with maximum clock frequency of ~80MHz. Here, we propose a FPGA based design of extremely high speed notch filter effectively operating at maximum clock frequency of ~1200MHz with the help of Scattered-Look-Ahead (SLA) pipelining with power-of-2- decomposition approach, proper retiming and unfolding applied over its basic low-speed structure. To generalize its FPGA based design for specific speed up factor, a new efficient simpler approach utilizing Pascal’s Triangle is proposed to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed notch filter.

Suresh Gawande, Sneha Bhujbal

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