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Analysis of Area � Delay Low Power Adders in QCA Using VHDL Code

Abstract

As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities.The physical limit can be overcome by using the approach quantum-dot cellular automata (QCA). In this brief, we propose a new adder that outperforms all state-of-theart competitors and achieves the best area-delay tradeoff. The 64-bit version of the novel adder spans over 18.72 μm2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases.

Ms.S.Rajalakshmi , Dr.P.Sampath, Mrs.K.Anitha

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