Novel Low-Power, Energy-Efficient Full Adder for Ultra Deep-Submicron Technology
Power consumption has emerged as a principle theme in today’s widely and frequently used portable electronics. The datapath consumes roughly 30% of the total power of a modern day high performance microprocessor. Adders are key components used in datapaths and, therefore, careful design and analysis is required for these units to obtain optimum performance So the full adder designs with low power characteristics are becoming more popular these days. This paper presents a novel low power, energy efficient full adder circuit implementation for ultra deep submicron design. With rapid technology scaling, the main focus in low power design is targeted to reduce the static power while trading other vital requirements such as driving capability, delay, total power and noise immunity. Based on the fact that transmission logic has good driving capability and full signal swing than pass transistor logic, a new full adder cell is proposed to reduce delay and power-delay product (PDP).The simulations have been carried out with TANNER EDA simulation tool using PTM 65nm technology files. Simulations have been carried out for different supply voltages and loading conditions to compare the performance of the proposed circuit with respect to the existing ones.
Jehangir Rashid Dar, Sajad Ahmad Ganiee