International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

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High Speed Multioutput 128bit Carry- Lookahead Adders Using Domino Logic

A.Bharathi1, K.Manikandan2, K.Rajasri3 and P.Santhini4
  1. PG Student [APPLIED ELECTRONICS], Dept. of ECE, IFET College of Engineering, Villupuram, Tamilnadu India
  2. Assistant professor, Dept. of ECE, IFET college of Engineering, Villupuram ,Tamilnadu, India
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Abstract

Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carry- look ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To overcome this drawback the domino circuits can be analysed and compared with 65nm technology is used. The proposed work is based on 256 bit Manchester Carry chain(MCC) adders compared with different CMOS technologies.

Keywords
Addition, Carry-Look ahead Adder (CLA), High Performance, propagation delay, CMOS technology, HSPICE tool

INTRODUCTION
In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic units, but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operation. The digital logic gates and circuits designed using dynamic domino technique is considerably faster than the logic gates and circuits designed with standard static logic style. Now four major performance parameters i.e. Power, area, delay and speed are focused by VLSI designer. A carry look ahead adder is a type of adder used in digital logic. It improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits.
In this paper Carry look ahead adder is designed and analyzed using standard CMOS technique. The Manchester carry chain adder (MCC) is the most popular dynamic (domino) CLA, is proposed with an implementation in VLSI. The MCC have enabled the development of multi-output domino gates which have given area and speed improvement with respect to single output. The efficiency of the MCC is trying to transfer its structure to static logic. In a report has been made of dynamic CMOS 4-bit CLA adder in multi-output logic which reduces the number of transistors which considered to a conventional schema. However, the simulation results not shown any speed improvement but reduce the delay.

RELATED WORK
The Basic operation of this model has the concept of carry look-ahead adders with a 4-bit as a input with an output of sum is generated and carry bits is propagated.
image
The CLA algorithm was first introduced in several variants have been developed. The Manchester carry chain (MCC) is the most common dynamic (domino) CLA adder architecture with a regular, fast, and simple structure adequate for implementation in VLSI[5] .The recursive properties of the carries in MCC have enabled the development of multioutput domino gates, which have shown area–speed improvements with respect to single-output gates using 90nm technology.
In this brief, a new 8-bit carry chain adder block in multi-output domino CMOS logic is proposed. The even and odd carries of this adder are computed in parallel by two independent 4-bit carry chains[7]. Implementation of wider adders based on the useof the proposed 8-bit adder module shows significant operating speed improvement compared to their corresponding adders based on the standard 4-bit MCC adder module[8].

NEW HIGH SPEED ADDER IN DYNAMIC(DOMINO) CIRCUIT
The generate signal implemented in domino logic is shown in Figure 2. It consists of two inputs namely ai and bi and has one output gi. The two inputs are connected in series thus perform AND operation. The operation of the circuit is controlled by clock signal.
image
The propagate signal implemented in domino logic is shown in Figure 3. It consists of two inputs ai and bi and consists of one output signal pi. Here the propagate signal is implemented in OR operation. The propagate circuit is controlled by clock signal. If clk goes to ‘0’, then the circuit will enter into precharge state and the output remains in 0 value. If clk value is 1, then the output value depends on input value. Since this propagate signal is OR operation based if any one of the inputs is 1, then output pi will maintain the value 1 else pi will have value 0.

SIMULATION RESULT AND DISCUSSION
In this section simulation results for carry look-ahead adder implemented in domino logic in 65nm technology. The following figures shows the simulation report with various parameter like power, voltage, temperature etc.,
image
image

CONCLUSION
In this paper the performance of 128-bit adder circuit designed using in dynamic (domino) circuit techniques is analysed in detail and its performance is compared with static adder circuits. The 128-bit adder circuit is simulated using L=65nm technology along with supply voltage VDD=1.0V. The experimental results shows that these adder circuits gives superior performance compared to adder circuits designed using conventional domino techniques. Further, Manchester carry chain adder in 256-bit is used for increasing high speed and reduced delay in the domino circuit.

References
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