Keywords
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            | hybrid fault current limiter, solid-state fault current limiters, superconducting fault current limiters       radial power distribution system. | 
        
        
            
            I. INTRODUCTION
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            | Over the past decades, superconducting technology have been grown in various area. Especially       superconducting fault current limiters have been developed. SFCL decreases the fault current and reduces the adverse       effect on the power system ultimately this can make the capacity of the circuit breakers small. Moreover, SFCL can       provide additional advantage as the improvement of voltage sag [1].Reference [1] presents the assessment method of       voltage sag using the Information of Technology Industry Council (ITIC) curve when SFCL is applied to radial power       distribution system. Reference [3] and [4] presents the improvement of voltage sag by installing the various fault       current limiters. Reference [13] presents the IGCT based solid-state fault current limiters. Reference [14] presents the       hybrid fault current limiter based on resonant LC circuit. Voltage sag is evaluated by magnitude and duration. In       general the series connected impedance such as SFCL improves the magnitude of sag where as it may worsen the       duration of sag because of the delayed trip time of the protective device by the decreased faults current. These effects of       various FCL on voltage distortion should be evaluated. In this paper we assess the impact of various types of FCL on       voltage distortion and fault current in radial power distribution system. In section II we model various types of FCL. In       section III the voltage distortion occurred by faulty current is explained and fault current magnitude is also analyzed. In       section IV we evaluate the voltage distortion magnitude using various FCL even we evaluate the fault current       magnitude using various fault current limiters. | 
        
        
            
            II. LITERATURE REVIEW
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            | In this paper we design the resistive type superconducting fault current limiter based on [1], [5]-[10]. The       impedance of SFCL according to time (t) is given in (1). Where Rn and tf represents the impedance being saturated at       normal temperature and time constant respectively. In addition to t1 , t2 represent quench start time, the first recovery       time and second recovery time | 
        
        
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            | The solid state fault current limiters developed by wanmin [13] consist of diodes, reactor and self turned- off       igct switches by optimizing the size of the inductor and with the introduction of switches that can handle high power,       this type of FCL can be made relatively compact in size. the author in [13] provides a good overview of the technical       detail involved in the model. the hybrid fault current limiter developed by h.arai [14] is based on the resonance       characteristics exhibited when an inductor and capacitor are in series with each other. the performance of various types       of fault current limiters are being analyzed on the basis of fault current limitation as well as limitation in the voltage       distortion during the occurrence of fault. the result of superconducting fault current limiter is being analyzed with solid       state as well as hybrid fault current limiters | 
        
        
            
            III. VOLTAGE DISTORTION AND FAULT CURRENT MAGNITUDE
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            | When fault occurs in a power distribution system the automatic reclosure or circuit breaker with over current relay       (OCR) and reclosing relay will open to clear the fault and automatically reclose after a time delay. This reclosure       behavior can take place several times in an effort to establish a continuous service when a temporary fault occurs       [11].Fig. 1 depicts the IEEE standard 6- bus system in PSCAD | 
        
        
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            | This IEEE model is stimulated in the PSCAD with the above mentioned specification as prescribed in the table and       various results are being analyzed Fig. 2 depicts the various fault current at various phases during the occurrence of       fault. Fig. 2 (a) depicts fault current in phase A, likewise Fig. 2 (b) depicts fault current in phases B and Fig. 2 (c)       depicts fault current in phase C | 
        
        
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            | When a fault occurs, the customer at each feeder experiences different magnitude of voltage according to various       factors such as line impedance, fault location and so on. Generally, a voltage magnitude at the bus near to the secondary       side of the main transformer during fault can be represented by the equation (2), ignoring the fault impedance and a       three phase fault is applied. The source voltage is at 1.0 p.u. | 
        
        
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            | Where Zsource , ZMtr and Zline are the source, line, transformer impedance from source to fault location respectively.       Equation (2) can also approximately represent the voltage magnitude at the customer on all the neighboring bus. In this       paper voltage magnitude is focused than duration. | 
        
        
            
            IV. ASSESSMENT OF IMPACT OF VARIOUS FCL
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            | A. Superconducting Fault Current Limiters | 
        
        
            | If SFCL is installed to the power distribution system, the equation (2) is changed to equation (3) during fault. The       voltage distortion is reduced than in the case without SFCL. | 
        
        
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            | The following segment explains the output waveforms obtained by the placement of various fault current       limiters at the optimal location in order to reduce the fault current as well as reduction in the voltage distortion that is       caused during the occurrence of fault. The current section discuss the performance of superconducting fault current       limiter followed by the performance analysis of other two types of fault current limiter i.e. Solid State fault current       limiter and Hybrid fault current limiter. The Fig. 4 and Fig. 5 depict the result obtained using superconducting fault       current limiter. Fig. 4 depicts the reduction in fault current in each phase under the influence of SFCL. Fig. 3 (a) depicts fault current in phase A, likewise Fig.3 (b) depicts fault current in phases B and Fig. 3 (c) depicts fault current in phase | 
        
        
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            | B. Solid-State Fault Current limitersq | 
        
        
            | The Fig 4 depict the impact of solid state fault current limiter on the fault current and the voltage distortion.       Fig. 6 depicts the fault current in each phase under the influence of solid state FCL. Fig. 4 (a) depicts fault current in       phase A, likewise Fig. 4 (b) depicts fault current in phases B and Fig.4 (c) depicts fault current in phase C. | 
        
        
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            | C. Hybrid Fault current limiter | 
        
        
            | The Fig.5 and depicts the impact of hybrid fault current limiter on the fault current and the voltage distortion. FCL.       Fig. 5 (a) depicts fault current in phase A, likewise Fig.5 (b) depicts fault current in phases B and Fig. 5 (c) depicts fault       current in phase C | 
        
        
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            V. CONCLUSION
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            | In this paper, a comprehensive up-to- date review of various types of fault current limiters are analyzed and the       behavior of each fault current limiters on the voltage distortion and the fault current limiting are also analyzed. From       the above discussion we conclude that SFCL is more efficient on the basis of both fault current limitation as well as       reducing the distortion in the voltage profile when comparing its performance with other two fault current limiters. | 
        
        
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            References
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