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An Efficient Design of Adder using Ultra Low Voltage CMOS Logic

Abstract

A static CMOS inverter does not dissipate power during the absence of transients on the input. During a transient in the input, there will be a time period in which both the NMOS Transistor and PMOS Transistor will conduct, causing a short circuit to flow from supply to ground for an inverter without load. For a CMOS circuit, the total power dissipation, includes dynamic and static components during the active mode of operation. To overcome the drawback of Complementary inverter, the ULV inverters are used in the design. The dynamic power consumption is reduced significantly with reduced supply voltage. The static power consumption is more dependent on the transistor threshold voltage. Scaling the supply voltage and threshold voltage reduces the dynamic power dissipation and static power dissipation respectively. In order to achieve high performance for low power consideration, the threshold voltage is scaled along with the supply voltage. The power consumption depends on the recharge voltage and the supply voltage. Therefore optimizing the supply voltage and recharge voltage results in reduced power consumption. Ultra Low Voltage Low Power CMOS Inverter the offset voltage is scaled along with the threshold voltage. The Ultra Low Voltage Inverter is configured to low power compared to that compared to that of a complementary inverter. A complementary inverter is designed using Tanner EDA Tool. The complementary inverter is used as the basic module for the design of the full adder. The power consumed by the full adder which is designed using the complementary inverter is calculated. Similarly, the Ultra Low Voltage Inverter is designed by Tanner EDA Tool. The Ultra Low Voltage Inverter is used as the basic module for the design of the full adder. The power consumed by the full adder which is designed using the Ultra Low Voltage Inverter is calculated. The objective is to prove that the power consumed by the Ultra Low Voltage Inverter is lower than that of the complementary inverter. Thus, the Ultra Low Voltage Inverter is configured to operate at low power compared to that of the complementary inverter. The logos presented here are designed for the 90nm process using Tanner EDA Tool.

P.Premkumar, S.Nandhini

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