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Power Efficient 3VL Memory Cell Design Using Carbon Nanotube Field Effect Transistors

Abstract

This paper presents a design of a 3VL memory cell using carbon nano-tube field-effect transistors (CNTFETs). 3VL is a promising alternative to conventional binary logic, as it has better performance in terms of area, power and also reduces interconnect delay. This cell uses a control gate for the write and read operation to make them separate. Transmission gate is used as control gate in this circuit. The CNTFET used for design has different threshold voltages to achieve ternary logic. This multi threshold voltage is obtained by varying the diameter of the CNT used. Chirality of the CNTFETs is utilized for varying the diameter of the CNT and it also avoids the usage of additional power supplies. The channel length used here is 18nm wide. The power consumption is reduced as there is absence of stand-by power dissipation. Second order effects are removed by using CNTFET in the circuit. The two memory operations, bit read and bit write operation of the proposed ternary cell perform correctly at 0.9V power supply. In a ternary system, it only takes log3 (2n) bits to represent an n-bit binary number. The proposed ternary memory cell achieves a significant saving in area compared with existing design since the λ rules are different for CNTFET. The parameters are measured using HSPICE.

S.Tamil Selvan, B.PremKumar, G.LAXMANAA

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