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ISSN ONLINE(2320-9801) PRINT (2320-9798)

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METAPHORICAL STUDY OF REVERSIBLE LOGIC GATES

Shweta Agrawal
M Tech [VLSI], Shri Ram College of Engineering and Management, Gwalior, India
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International Journal of Innovative Research in Computer and Communication Engineering

Abstract

In today’s world power dissipation is the main problem in digital world; this problem can be reduced by using reversible logic gates. For high performance systems, low power and smaller area are the most important criteria. Area and speed are main factors which are conflicting i.e. if speed is improving it results in larger area, hence in this paper reversible logic gates are analyzed. The power dissipation by these gates is very low; ideally their internal power dissipation is zero because these gates do not loss information. Systems where low power dissipation is required reversible logic gates will be used in place of classical logical gates like AND, OR, NAND, NOR. Reversible logic provides an alternative that may overcome many of these problems in the future. By reducing the number of reversible logic gates one can minimize the quantum cost of these gates. Reversible logic finds its application in low power CMOS, quantum computing, nanotechnology, bio-information etc

Keywords
Reversible logic, Reversible logic gate, quantum computing, nanotechnology.

INTRODUCTION
The main aim of VLSI Circuit Design is very low power dissipation and improves system performance. According to R.Landauer researcher there is power dissipation of KTln2 joules of heat energy per bit of information loss in classical gates, where K is Boltzmann’s constant and T the absolute temperature at which circuit performs [1].
Reversible logic does not loss any information. Reversible logic gate are the device which has n×n inputs and outputs, its means input is equal to output or there is one to one mapping. Any gate is said to be reversible if the input can be recovered from the output.

A Reversible circuit has the facility to generate a unique output vector from each input vector, and vice versa.
Input Vector
image
Output Vector
image
For each particular vector j
Iv⇔Ov
Reversible are circuits in which the number of inputs is equal to the number of outputs and there is one-to-one mapping between vectors of inputs and outputs.

Difference between Reversible Gate and Irreversible Gate
Features of reversible logic:
1. One to one mapping i.e. equal no of input and output.
2. For each input there is different output.
3. Fan out is not allowed.
Features of reversible logic circuit [6]:
1. Minimum number of reversible gates is used.
2. Minimum number of constant inputs is used.
3. Minimum number of garbage outputs should be there.
4. The length of cascading gates is minimum.
Basic Reversible logic Gates:
• N= No. Of reversible logical gate used in circuit.
• CI= No. of inputs that are at constant 0 or 1 for synthesis of any given logical functions.
• GO= No. of unused outputs in reversible logic.

TYPES OF REVERSIBLE LOGIC GATES
1. Feynman Gate: It is a 2×2 reversible gate. A, B is input vector and P, Q is output vector. The output P=A, Q=A⊕B. It is used where copying is required and inverter both at the same time due to its output. The block diagram of this gate is shown in Fig .1
2. Double Feynman Gate (F2G): It is 3×3 Double Feynman gate. A, B, C are input vector and P, Q, R are output vector, where P = A, Q=A⊕B and R=A⊕C. The block diagram of this gate is shown in Fig.3
3. Toffoli Gate: It is 3×3 reversible logic gate having A,B,C as input vector and P,Q ,R as output vector, where P=A,Q=B and R=AB ⊕ C The block diagram of this gate is shown in Fig.5
4. Fredkin Gate :It is 3×3 reversible logic gate having A,B,C as input vector and P,Q,R as output vector, where P=A,Q=A’B⊕AC , R=A’C⊕AB The block diagram of this gate is shown in Fig.8
5. Peres Gate: It is 3×3 reversible logic gate. A, B, C is input vector and P, Q, R is output vector, where P = A, Q = A⊕B and R=AB⊕ C. The block diagram of this gate is shown in Fig.9
6. TSG gate: It is 4×4 reversible gate. A, B, C, D is input vector and P, Q, R, S is output vector, output P = A, Q = A’C’&B’, R = (A’C’&B’) & D and S = (A’C’&B’).D⊕ (AB⊕C), the block diagram of this gate is shown in Fig.11
7. Sayem gate: It is 4×4 reversible gate. A, B, C, D is input P, Q, R, S is output vector, where P=A, Q=A’B& AC, R= A’B &AC& D, S=AB &A’C & D). The block diagram of this gate is shown in Fig.13

III. APPLICATIONS
Reversible logic finds its application in computer security and transaction processing, as it possess high energy efficiency, speed and performance.

IV. CONCLUSION
The paper reveals that reversible logic gates outperform classical logic gates. The prospect for further research includes quantum computing and Nano technology.

ACKNOWLEDGMENT
We take this opportunity to express our deepest gratitude and appreciation to all those who have helped us directly or indirectly towards the successful completion of this paper.

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